Flop_n_Adder - The Digital Design Mentor
Flop_n_Adder, led by Dr. Rachna Srivastava (PhD, University of Waterloo), simplifies complex digital and ASIC design concepts for engineers and students. Combining deep semiconductor expertise with clear, structured explanations, she helps learners bridge the gap between academic theory and industry practice.
About Rachna
Dr. Rachna Srivastava is an ASIC and FPGA design expert with over 20 years of combined academic and industry experience. Currently with Ciena, she has previously worked with Axiado Corporation, Intel Technology India, and STMicroelectronics. Her work spans ASIC design workflows, timing, noise, and power characterization, as well as teaching and research in digital systems and neural recording ICs. She holds a PhD and MASc in Electrical and Computer Engineering from the University of Waterloo and a BE in Electronics and Communication from Deendayal Upadhyay Gorakhpur University. Through her YouTube channel, Flop_n_Adder, she demystifies integrated circuit and digital design concepts for students and engineers worldwide, blending academic rigor with hands-on clarity. Her unique value lies in bridging research-level understanding with real-world semiconductor engineering practices.
22+ Years of Professional Experience
Areas of Expertise
ASIC Design and Verification
FPGA Architecture and Implementation
CMOS Circuit Design and Analysis
Timing, Power, and Noise Characterization
Static Timing Analysis and Clock Skew
Low-Power VLSI Design
SRAM and Memory Circuit Design
Signal Processing Hardware
Digital Logic Design (Setup-Hold Timing)
Synthesis and RTL Coding (Mentor, Intel Quartus)
Simulation Tools (Hspice, Eldo, ModelSim)
Power and Noise Simulation (RedHawk, VoltageStorm)
Hardware Description Languages (VHDL, Verilog)
Programming (MATLAB, C, Perl, Shell, Git)
ASIC Design Flow and Verification Methodology
Education & Certifications
- PhD, Electrical and Computer Engineering, University of Waterloo
- MASc, Electrical and Computer Engineering, University of Waterloo
- BE, Electronics and Communication Engineering, MMMUT, India
Achievements & Recognition
- Alexander Graham Bell Canada Graduate Scholarship (CGS-M)
- President’s Graduate Scholarship, University of Waterloo
Who Can Benefit
VLSI Aspirant
Undergraduate or graduate students pursuing electronics, communication, or VLSI design who seek conceptual clarity and industry-level understanding.
- Learn CMOS and ASIC fundamentals clearly
- Prepare for semiconductor industry interviews
- Build confidence in digital design concepts
- Bridge the gap between theory and practical applications
Early-Career Chip Designer
Entry-level professionals in semiconductor firms aiming to refine their technical and timing analysis skills.
- Strengthen design-for-timing and verification knowledge
- Understand best practices for ASIC design flow
- Improve power and noise analysis skills
- Gain exposure to advanced CMOS design principles
Research Engineer / PhD Student
Researchers or doctoral candidates exploring hardware architectures, low-power circuits, or signal processing in hardware.
- Translate theoretical ideas into working hardware
- Explore FPGA-based implementation of algorithms
- Understand LDLC and other advanced circuit techniques
- Stay current with ASIC verification methodologies
Educator / Teaching Assistant
University instructors or TAs teaching digital systems or VLSI courses who seek teaching inspiration or examples.
- Simplify complex digital design topics for students
- Find concise explanations of CMOS and ASIC fundamentals
- Adopt structured teaching styles for online education
- Stay aligned with evolving semiconductor education methods
Tech Enthusiast / Career Switcher
Professionals from adjacent domains (e.g., embedded systems, software) exploring a transition into chip design.
- Grasp ASIC and FPGA basics quickly
- Understand circuit behavior intuitively
- Identify entry-level pathways into semiconductor roles
- Get familiar with industry-standard tools and workflows